FIG. 1 is a schematic circuit block diagram illustrating a conventional digital D latch. As shown in FIG. 1, the conventional digital D latch 100 comprises a first stage circuit 102, a second stage circuit 104, and an inverter 106. A clock signal CK is inputted into a clock input terminal ck2 of the second stage circuit 104. Moreover, the clock signal CK is also inputted into the inverter 106, so that an inverted clock signal CK is outputted from the inverter 106. The inverted clock signal CK is inputted into a clock input terminal ck1 of the first stage circuit 102. The first stage circuit 102 may be considered as a master latching circuit, and the second stage circuit 104 may be considered as a slave latching circuit.
In response to a first voltage level (e.g. a low voltage level) of the clock signal CK and a second voltage level (e.g. a high voltage level), the first stage circuit 102 is enabled, but the second stage circuit 104 is disabled. Meanwhile, a logic level of an input signal D is transmitted from an input terminal d1 of the first stage circuit 102 to an output terminal q1 of the first stage circuit 102. Consequently, in response to the first voltage level of the clock signal CK, the input signal D and an output signal O1 of the first stage circuit 102 have the same logic level.
In response to the second voltage level (e.g. the high voltage level) of the clock signal CK and the first voltage level (e.g. the low voltage level), the first stage circuit 102 is disabled, but the second stage circuit 104 is enabled. Meanwhile, regardless of whether the input signal D is changed or not, the output signal O1 of the first stage circuit 102 is maintained at the original logic level. In addition, after the output signal O1 of the first stage circuit 102 is inputted into an input terminal d2 of the second stage circuit 104, an output signal O2 is outputted from an output terminal q2 of the second stage circuit 104. The output signal O2 of the second stage circuit 104 is an output signal Q of the digital D latch 100.
From the above discussions, the clock signal CK and the input signal D of the conventional digital D latch 100 are standard logic levels. In case that the frequency of the clock signal CK is not very high, the conventional digital D latch 100 can be normally operated. However, when the frequency of the clock signal CK is up to the GHz level, the conventional digital D latch 100 is usually abnormal.
Therefore, there is a need of providing a current-mode D latch that is operable at a high frequency and has a reset function.